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NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
July 1998
NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
General Description
The NM95MS16 is the smaller of a family of devices designed to provide complete Plug and Play Capability for ISA bus systems. The NM95MS16 includes the necessary state machine logic to manage the Plug and Play protocol in addition to switches for steering Interrupt and DMA requests. It also features a built-in 2 kbits of serial EEPROM for storing the resource data specified in the Plug and Play Standard. In addition, 4 kbits of EEPROM is available for use by other on-board logic. This device provides a "truly complete" single-chip solution for implementing Plug and Play on ISA-Bus Adapter cards. The NM95MS16 supports one logical device with a flexible choice of DMA/IRQ selection and I/O Chipselect generation as well as offering 16-bit addressing in Mode 1. NM95MS16 is implemented using Fairchild's Advanced CMOS process and operates single power supply. The NM95MS16 is available in a 48-pin TQFP package and 52-pin PLCC package.
Features
s Complete Implementation of Plug and Play Standard -- Direct interface to ISA bus s Two modes of operation -- DMA mode -- Extended Interrupt mode (Windows(R) 95 logo compatible) s 6 or 8 ISA bus interrupt lines and 2 DRQ/DACK lines supported s On-chip EEPROM for resource request table s Additional 4 kbits of on-chip EEPROM available for external access s 24 mA Drivers for Data outputs s Complete compliance to ISA PnP specification (Ver. 1.0A) s 48-Pin TQFP, and 52-Pin PLCC Packages
Block Diagram
Osc. Rstdrv From ISA Bus Address Control
State Machine
EEPROM
MICROWIRE Port
Decoder & Control
Register Block
Data Buffer
SD<0:7>
ISA Bus
Address From ISA Bus Control DACKx* LIRQx LDRQx Function Module Support Logic IOCS<0:2>* LDACKx* IRQx DRQx
To ISA Bus
DS012601-1
Windows(R) 95 is a registered trademark of Microsoft Corporation.
(c) 1998 Fairchild Semiconductor Corporation
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NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
Connection Diagrams Commercial Temperature Range (0C to +70C)
DACKOUT*/IOCS2* IRQIN1/SA14 DRQIN/SA15
IRQOUT5
IOCS0*
12
11
10
9
8
7
6
5
4
3
IOCS1*
2
IRQIN0
IOWR*
IORD*
GND
VCC
RSTDRV
1 48 47 46 45 44 43 42 41 40 39 38 37
IRQOUT4 IRQOUT3 IRQOUT2 IRQOUT1 IRQOUT0 ISADRQ0/IRQOUT6 ISADRQ1/IRQOUT7 ISADACK0*/SA12 ISADACK1*/SA13 CS SK SA0
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 OSC AEN DO DI
NM95MS16 (TQFP)
SA1
SA2
SA10
SA11
SA3
SA7
GND
SA4
SA5
SA6
SA8
SA9
DS012601-2
Order Number NM95MS16VBH
DACKOUT*/IOCS2*
DRQIN/ISA15
IRQOUT5
IRQIN1/SA14
7 IRQOUT4 IRQOUT3 IRQOUT2 IRQOUT1 IRQOUT0 ISADRQ0/IRQOUT6 NC ISADRQ1/IRQOUT7 ISADACK0*/SA12 ISADACK1*/SA13 CS SK SA0 8 9 10 11 12 13 14 15 16 17 18 19 20 21
6
5
4
3
2
1
52 51
50 49 48 47 46 45 44 43 42
IOCS0*
IOCS1*
IOWR*
RSTDRV
IRQIN0
VCC
IORD*
GND
NC
SD7 SD6 SD5 SD4 SD3 SD2 NC SD1 SD0 OSC AEN DO DI
NM95MS16 (PLCC)
41 40 39 38 37 36 35
22 23
24 25 26 27
28 29
34 30 31 32 33
SA2
SA3
SA1
SA6
SA9
SA10
SA8
SA11
SA4
SA5
NC
GND
SA7
DS012601-3
Order Number NM95MS16V
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NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
Connection Diagrams (Continued)
Signals
SA<11:0> IORD* IOWR* AEN SD<7:0> OSC (Note 1) RSTDRV CS
Type
I I I I I/O I I I
Description
Address inputs from the ISA bus. I/O read strobe from the ISA bus. I/O write strobe from the ISA bus. Address Enable from ISA Bus --used in conjunction with DMA. Data bus --lower byte --from/to the ISA bus. "OSC" clock from the ISA bus --used for internal state machines. Reset input from the ISA bus. Chip select for Microwire port. There should be a pull down resistor of 4.7k on CS pin if unused externally, or directly connected to GND. Clock and Data input lines for Microwire bus connection to access a portion (4k) on chip EEPROM. Data output line for the Microwire interface detailed above. Connection to ISA bus interrupt request pins. On-chip interrupt request(s) may be connected to any 6 of the ISA IRQ lines. Interrupt request from on-board logic DMA request from on-board logic, or Address input from ISA bus depending on mode selected. DMA Acknowledge for on-board logic or Programmable chipselect (2) depending on mode selected. Connection for two ISA bus DMA Request lines, or additional interrupt request lines depending on the mode selected. DMA Acknowledge from the ISA bus or additional address lines depending on the mode selected. Programmable chip selects to address on-board peripheral. Interrupt request from on board logic or Address input from ISA bus depending on mode selected.
SK, DI DO IRQOUT<5:0> IRQIN<1:0> DRQin/SA<15> DACKOUT* /IOCS2* ISADRQ<1:0>/IRQOUT<7:6> ISADACK<1:0>*/SA<13:12> IOCS<1:0>* IRQIN<1>/SA<14>
I O O I I O O I O I
*Signal name with a "*" means its an active low signal. Note 1: "OSC" clock from ISA Bus is fixed at a standard frequency of 14.318 MHz. NM95MS16 is designed and tested for 14.318 MHz. However NM95MS16 can handle frequencies up to 24 MHz though it is not 100% tested.
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NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
Pinout Details for the NM95MS16
Mode 00 = DMA Mode; Mode 01 = Extended Interrupt Mode
TQFP Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Note:
DMA Mode
RSTDRV IOCS1* IOCS0* IORD* IOWR* VCC DRQIN DACKOUT* GND IRQIN1 IRQIN0 IRQOUT5 IRQOUT4 IRQOUT3 IRQOUT2 IRQOUT1 IRQOUT0 ISADRQ0 ISADRQ1 ISADACK0* ISADACK1* CS SK SA0
Ext.Intr.Mode
RSTDRV IOCS1* IOCS0* IORD* IOWR* VCC SA15 IOCS2* GND SA14 IRQIN0 IRQOUT5 IRQOUT4 IRQOUT3 IRQOUT2 IRQOUT1 IRQOUT0 IRQOUT6 IRQOUT7 SA12 SA13 CS SK SA0
TQFP Pin
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
DMA Mode
SA1 SA2 SA3 SA4 GND SA5 SA6 SA7 SA8 SA9 SA10 SA11 DI DO AEN OSC SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
Ext.Intr.Mode
SA1 SA2 SA3 SA4 GND SA5 SA6 SA7 SA8 SA9 SA10 SA11 DI DO AEN OSC SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
Mode selection (00 or 01) is done by setting MS bits in the EEPROM configuration register. Detailed information about this is described in User's Guide.
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NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
Absolute Maximum Ratings (Note 2)
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating -65C to +150C VCC + 1V to -0.3V +300C 2000V Min
Operating Conditions
Ambient Operating Temperature NM95MS16 Positive Power Supply (VCC) 0C to +70C 4.5V to 5.5V
DC Electrical Characteristics
Symbol Parameter Test Conditions Min ICCA ILI ILO VIL VIH VOL VOH Active Power Supply Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 24 mA (Note 5) IOL = 2.1 mA (Note 6) IOH = -3 mA (Note 5) IOH = -400 A (Note 6) 2.4 2.4 fSCL = 100 kHz VIN = GND or VCC VOUT = GND to VCC -0.1 2.0 0.8 0.2 Limits Typ (Note 3) Units Max 15 15 15 V VCC + 1.0 0.4 V V V V mA A A
Capacitance TA = +25C, f = 1.0 MHz, VCC = 5V
Symbol
CI/O (Note 4) CIN (Note 4) COUT (Note 4)
Test
Input/Output Capacitance Input Capacitance Output Capacitance
Conditions
VI/O = 0V VIN = 0V VOUT = 0V
Max
8 6 6
Units
pF pF pF
Note 2: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 3: Typical values are for TA = 25C and nominal supply voltage (5V). Note 4: This parameter is periodically sampled and not 100% tested. Note 5: These values are for ISA signals like SD[0:7], IRQx, DRQx. Note 6: These values are for card signal like IOCS[0:3]*, DO(EEPROM).
AC Electrical Characteristics
Symbol
tAEN tAC tRVD tAH tRDH tWD tWDH tCSA tCSC tIDD
Parameter
AEN Valid to Command Active Address Valid to Command Active Active Read to Valid Data Address, AEN Hold from Inactive Command Read Data Hold from Inactive Read Write Data Valid before Write Active Write Data Hold after Write Inactive Chip Selects Valid from Address Valid Chip Selects Valid from Command Active Propagation Delay for IRQ/DRQ/DACK
Min
100 88
Max
Unit
ns ns
200 30 5 22 25 5 5 5 25 25 25
ns ns ns ns ns ns ns ns
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NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
Timing Diagrams
Timings for ISA Read/Write Cycle
AEN tAEN SA[0:11] tAC IORD* IOWR* READ DATA SD[0:7] WRITE DATA SD[0:7] tWDH
DS012601-4
tAH VALID ADDRESS tRVD VALID tWD tRDH
Decode Delay for Chipselect Generation
tCSA SA[0:11] IOCS[0:1]* (addr decode only) tCSC IORD* IOWR* IOCS[0:1]* (Qualified with CMD)
DS012601-5
tCSA VALID ADDRESS
tCSC
Propagation Delay for IRQ/DRQ/DACK
IRQin DRQin ISADACK IRQout DRQout DACKout
tIDD
tIDD
DS012601-6
INTRODUCTION
The NM95MS16 is a single-chip solution for the ISA Plug and Play (PnP) specification. It implements the complete state machine and the necessary logic for supporting configurable Interrrupts and DMA channels on the ISA bus for one logical device. Apart from providing "PnP" capability, it has built-in EEPROM that eliminates external EEPROM. This device is available in a space saving 48-pin Thin Quad Flat Pack (TQFP) package.
(Refer to the NM95MS16 User's guide for detailed information). Each of these modes are discussed below.
DMA Mode
In the DMA mode, support is provided for 1. One on-board DMA request that is switchable to any two DMA channels on the ISA bus. 2. Two on-board interrupt request lines switchable to any six IRQ lines on the ISA bus. 3. Two programmable I/O chip selects for on-board logic. Figure 1 shows a Block Diagram of NM95MS16 configured for DMA Mode.
Functional Description
NM95MS16 has two modes of operation, viz, "DMA mode" and "Extended Interrupt mode". These modes are programmed using the mode select (MS) bits in one of the configuration registers
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NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
INTRODUCTION (Continued)
FUNCTION MODULE
SCSI/MODEM/ETHERNET CONTROLLERS
IRQIN0 IRQIN1 2
DRQIN DACKOUT* 2 IOCS[0:1] CS,SK,DI
2
NM95MS16
(DMA Mode)
3
EEPROM
DO
RSTDRV OSC SA[0:11] 12 SD[0:7] 8 IORD* IOWR* 3 AEN IRQOUT 6 [0:5] DRQ 2 [0:1] DACK 2 [0:1]
ISA BUS
DS012601-7
FIGURE 1. Extended Interrupt Mode
In the Ext.Int. mode, support is provided for: 1. Two on-board interrupt request lines switchable to any eight IRQ lines on the ISA bus. 2. Three programmable I/O chip selects for on-board logic. 3. ISA address SA12-SA15 are also included for extended decode. Figure 2 shows a Block Diagram of NM95MS16 configured for Extended Interrupt Mode.
FUNCTION MODULE
SERIAL I/O /MULTI-MEDIA CONTROLLERS
IRQIN0 1 4 IOCS[0:2] CS,SK,DI
2
NM95MS16
(Extended Interrupt Mode)
3
EEPROM
DO
RSTDRV OSC SA[0:15] 16 SD[0:7] 8 IORD* IOWR* 3 AEN IRQOUT 8 [0:7]
ISA BUS
DS012601-8
FIGURE 2.
Chipselect Generation
Individual I/O chipselect can be generated in the following two ways: A) Address Decode only B) Address Decode qualified by Command (IORD*, IOWR*).
On-Chip EEPROM
NM95MS16 has 6 kbits of EEPROM on chip. All the PnP resource data structure for the logical device is stored in this EEPROM. Of the 6 kbits, 4 kbits are available for the logical device's external usage. The logical device can access the EEPROM through a microwire port, which is essentially a 4-wire serial bus. The pins CS, SK, DI and DO follow the exact timing as the standard microwire bus and are compatible to the NM93Cxx family of EEPROMs.
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NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
INTRODUCTION (Continued)
EEPROM Programming
The entire 6 kbits of EEPROM can be programmed through the ISA bus. The EEPROM can be programmed by putting the device (NM95MS16) in the Config. state (as defined in the PnP standard). Under this state 4 registers at address 0xF0-0xF3 are accessible to program the EEPROM. The data to be programmed is loaded in register at address 0xF3 and 0xF2 (LSB and MSB respectively). The address to be programmed is loaded in register at address 0xF1. The Ninth bit of address for 6 kbits of memory is provided through the register at address 0xF0. Both read write are possible. The actual operation does not begin until Go Ahead (GA) bit is set. Programming a word takes approximately 10 ms. The status of the operation can be polled by the Status bit. This bit is set when the operation is in progress and will be reset when complete. The register at address 0xF0 is COMMAND register. This is the handshake register in programming the EEPROM and is explained below in a tabular format.
COMMAND Register
0xF0
Bit[1:0]
--OP Code bits
10 - Read operation 01 - Write operation 11 - Erase operation
Bit[2] Bit[6:3] Bit[7] Address Register Data Register Data Register STATUS Register 0xF1 0xF2 0xF3 0x05
--GA(Go ahead bits) If set to 1 the programming will continue. --Reserved, should be 0. --It provides A8 of the address. A[0:7] is provided by 0xF1 reg. (Note 7)
AddressRegister [A0-A7] Data Byte [MSB] Data Byte [LSB] Bit[0] --Status/Busy bit. "0" if busy, "1" is done.
Note 7: The PNP resource data portion of the internal memory is at high address. Hence to program that portion, bit [7] of register 0xF0 (Address A8) should be set to "1".
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NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
Physical Dimensions inches (millimeters) unless otherwise noted
0.750 - 0.756 [19.05 - 19.20] 0.013-0.021 TYP [0.33-0.53] 1 52 47 46 0.026-0.032 TYP [0.66-0.81] 0.690-0.730 TYP [17.53-18.54] 45X0.045 [1.14]
Pin 1 IDENT 7 8
45 X 0.045 [1.14]
20 21 0.050 TYP [1.27] 0.600 [15.24] TYP 33
34 0.020 MIN TYP [0.51] 0.090-0.130 TYP [2.29-3.30] 0.165-0.180 TYP [4.19-4.57]
0.785 - 0.795 [19.94 - 20.19]
52-Lead Molded Plastic Leaded Chip Carrier Package Number V52A Order Number NM95MS16V
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NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems
Physical Dimensions inches (millimeters) unless otherwise noted
9.0 0.25 Typ 1.0 36 25 0 Min R 0.08 - 0.20 Gage plane 0.25
0- 7
12 Top and Bottom
37
24
1.6 MAX
Seating Plane 0.08 DETAIL A Typical 0.05 - 0.10
48
13
0.60 0.15
Pin #1 Ident
1
12 0.5 Typ.
0.20 Min Optional: Sharp corners except Pin #1 Ident corner
See Detail A
1.40 0.05
0.125 Typ
7.0 0.1
TQFP Package (VBH) Package Number VBH48A Order Number NM95MS16VBH
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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